SynTest Receives a Patent for Eliminating Unpredictability of ATPG Capture Results Due to Unknown ('X') Values When Using Test Compression; "Mask Network Design for Scan-Based Integrated Circuits"
SAN JOSE, Calif.—(BUSINESS WIRE)—April 25, 2006—
SynTest Technologies, Inc., a leading supplier of
Design-for-Test (DFT) tools, was granted 76 claims on April 18, 2006
under United States patent number 7,032,148 for its invention of
selectively masking off unknown ('X') captured scan data in first
selected scan cells from propagating through the scan chains.
The patented invention are methods and apparatus for selectively
masking off unknown ('X') captured scan data in scan cells from
propagating through the scan chains for test, debug, diagnosis, and
yield improvement of a scan-based integrated circuit in scan-test mode
or self-test mode. The method and apparatus further includes an
output-mask controller and an output-mask network embedded on the scan
data input path of scan cells, or a set/reset controller controlling
set/reset inputs of selected scan cells. A synthesis method is also
proposed for synthesizing the output-mask controller and the set/reset
controller. The patented inventions are used in SynTest products
VirtualScan for ATPG pattern compression and TurboBIST-Logic for
self-test, in use worldwide today, resulting in improved yield,
productivity and time-to-market (TTM). The patented inventions also
aid in improved debug and diagnosis of integrated circuit.
About SynTest
SynTest Technologies, Inc., established in 1990, develops
intellectual properties (IPs) for advanced design-for-test (DFT) and
design-for-debug/diagnosis (DFD) applications and markets them
throughout the world, to semiconductor companies, system houses and
design service providers. The company has filed more than 25 US/PCT
patents of which 4 have been issued and 2 allowed. The Company's
products improve an electronic design's quality and reduce overall
design and test costs. Various applications that use these IPs include
logic BIST, memory BIST, boundary-scan synthesis, scan/ATPG with test
compression, concurrent fault simulation, silicon debug and diagnosis.
The company, headquartered in Sunnyvale, California, has offices in
Taiwan, Japan, Korea and China, and distributors in Europe and Asia
including Israel. More information is available at www.syntest.com.
SynTest Technologies, Inc. is headquartered at 505 South Pastoria
Ave., Suite 101, Sunnyvale, California 94086, Phone: 408-720-9956,
E-Mail: info@syntest.com.
SynTest VirtualScan and TurboBIST-Logic are trademarks of SynTest
Technologies, Inc. All other trademarks are property of their
respective owners.
Acronyms:
ATPG: Automatic Test Program Generation
BIST: Built-In Self-Test
DFT: Design-for-Test
DFD: Design-for-Debug/Diagnosis
IP: Intellectual Property
TTM: Time-to-Market
Contact:
SynTest Technologies, Inc.
Ravi Apte, 408-720-9956 ext. 300
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